Data hazards occur when data is used before it is ready. With respect to memory access, data hazards may occur when two memory access instructions having data dependency are in the execution pipeline at the same time. An example of such data dependency may be when a vector load instruction and a vector store instruction access the same memory region or overlapping memory regions. Data hazards caused by memory access instructions include Read-After-Write (RAW) hazards and Write-After-Read (WAR) hazards.
A WAR hazard occurs when a store instruction follows a load instruction, both accessing the same memory location. A RAW hazard occurs when the load instruction follows the store instruction. To prevent these hazards, one conventional solution checks memory address range used by the memory access instructions. The memory range for a vector load/store instruction can be defined by a start point, end point and length. If there is an overlap in the memory ranges accessed by a vector load/store pair, the latter memory access is stopped until the first one is complete. However, the range-checking mechanism in large memory addressing space is usually tedious and time-consuming. Memory pointers may be resolved at a late pipeline stage, which further delays the latter memory access. When there are multiple instructions in the various pipelines stages of function units, the complexity range-checking logics may grow exponentially thereby significantly increasing hardware cost.
Another conventional solution is to set a memory barrier during the execution of a memory access instruction. All of the subsequent instructions, whether or not having data dependency with the instruction being executed, are stalled. The memory barrier causes significant performance degradation because it places a broad range of the processor's function units and data path pipelines in an idle state. The memory barrier is also inefficient, because some of the stalled instructions cannot be executed even though they may have no data dependency with the currently-executed instruction.